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ltc3407a-2 1 3407a2f high efficiency: up to 95% low ripple (<35mv pk-pk ) burst mode operation; i q = 40 a 2.25mhz constant frequency operation no schottky diodes required low r ds(on) internal switches: 0.35 current mode operation for excellent line and load transient response short-circuit protected low dropout operation: 100% duty cycle ultralow shutdown current: i q <1 a output voltages from 5v down to 0.6v power-on reset output externally synchronizable oscillator optional external soft-start small thermally enhanced msop and 3mm 3mm dfn packages applicatio s u features typical applicatio u descriptio u pdas/palmtop pcs digital cameras cellular phones wireless and dsl modems dual synchronous 800ma, 2.25mhz step-down dc/dc regulator the ltc ? 3407a-2 is a dual, constant frequency, synchro- nous step-down dc/dc converter. intended for low power applications, it operates from a 2.5v to 5.5v input voltage range and has a constant 2.25mhz switching frequency, enabling the use of tiny, low cost capacitors and inductors 1mm or less in height. each output voltage is adjustable from 0.6v to 5v. internal synchronous 0.35 , 1a power switches provide high efficiency without the need for external schottky diodes. a user selectable mode input is provided to allow the user to trade-off ripple noise for low power efficiency. burst mode ? operation provides the highest efficiency at light loads, while pulse skip mode provides the lowest ripple noise at light loads. to further maximize battery life, the p-channel mosfets are turned on continuously in dropout (100% duty cycle), and both channels draw a total quiescent current of only 40 a. in shutdown, the device draws <1 a. efficiency/power loss curve 1mm high 2.5v/1.8v at 800ma step-down regulators run/ss2 v in v in = 2.5v to 5.5v v out2 = 2.5v at 800ma v out1 = 1.8v at 800ma run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 10 f 100k reset 22pf 22pf 2.2 h 2.2 h 887k 887k 442k 280k 10 f 10 f 3407a2 ta01 , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. load current (ma) 1 0 efficiency (%) power loss (w) 30 20 10 70 60 50 40 100 0.0001 0.001 0.1 0.01 1 90 80 10 100 1000 3407a2 ta02 2.5v v in = 3.3v burst mode operation no load on other channel 1.8v
ltc3407a-2 2 3407a2f v in voltage .................................................. e 0.3v to 6v v fb1 , v fb2 voltages................................... e 0.3v to 1.5v run/ss1, run/ss2 voltages ..................... e 0.3v to v in mode/sync voltage .................................. e 0.3v to v in sw1, sw2 voltages ....................... e 0.3v to v in + 0.3v por voltage ................................................e 0.3v to 6v absolute axi u rati gs w ww u (note 1) operating temperature range (note 2) ltc3407ae-2 ..................................... e 40 c to 85 c ltc3407ai-2 .................................... e 40 c to 125 c junction temperature (note 5) ............................. 125 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec) ltc3407aemse-2 ............................................ 300 c ltc3407aimse-2 ............................................. 300 c t jmax = 125 c, v ja = 45 c/w, v jc = 10 c/w exposed pad (pin 11) is pgnd, must be connected to gnd lead free finish tape and reel part marking* package description temperature range ltc3407aedd-2#pbf ltc3407aedd-2#trpbf lddh 10-lead (3mm 3mm) plastic dfn e 40 c to 85 c ltc3407aemse-2#pbf ltc3407aemse-2#trpbf ltddj 10-lead plastic msop e 40 c to 85 c ltc3407aidd-2#pbf ltc3407aidd-2#trpbf lddh 10-lead (3mm 3mm) plastic dfn e 40 c to 125 c ltc3407aimse-2#pbf ltc3407aimse-2#trpbf ltddj 10-lead plastic msop e 40 c to 125 c lead based finish tape and reel part marking* package description temperature range ltc3407aedd-2 ltc3407aedd-2#tr lddh 10-lead (3mm 3mm) plastic dfn e 40 c to 85 c ltc3407aemse-2 ltc3407aemse-2#tr ltddj 10-lead plastic msop e 40 c to 85 c ltc3407aidd-2 ltc3407aidd-2#tr lddh 10-lead (3mm 3mm) plastic dfn e 40 c to 125 c ltc3407aimse-2 ltc3407aimse-2#tr ltddj 10-lead plastic msop e 40 c to 125 c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pi co figuratio uuu order i for atio uu w t jmax = 125 c, v ja = 45 c/w, v jc = 10 c/w exposed pad (pin 11) is pgnd, must be connected to gnd top view 1 2 3 4 5 v fb1 run/ss1 v in sw1 gnd 10 9 8 7 6 v fb2 run/ss2 por sw2 mode/sync 11 mse package 10-lead plastic msop top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v fb2 run/ss2 por sw2 mode/sync v fb1 run/ss1 v in sw1 gnd 11
ltc3407a-2 3 3407a2f electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.6v, unless otherwise specified. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3407ae-2 is guaranteed to meet specified performance from 0 c to 85 c. specifications over the C 40 c and 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3407ai-2 is guaranteed over the full C40 c to 125 c operating temperature range. note 3: the ltc3407a-2 is tested in a proprietary test mode that connects v fb to the output of the error amplifier. note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ). note 6: the dfn switch on-resistance is guaranteed by correlation to wafer level measurements. symbol parameter conditions min typ max units v in operating voltage range 2.5 5.5 v i fb feedback pin input current 30 na v fb feedback voltage (note 3) 0 c t a 85 c 0.588 0.6 0.612 v C40 c t a 125 c (note 2) 0.585 0.6 0.612 v v line reg reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.3 0.5 %/v v load reg output voltage load regulation mode/sync = 0v (note 3) 0.5 % i s input dc supply current (note 4) active mode v fb1 = v fb2 = 0.5v 700 950 a sleep mode v fb1 = v fb2 = 0.63v, mode/sync = 3.6v 40 60 a shutdown run = 0v, v in = 5.5v, mode/sync = 0v 0.1 1 a f osc oscillator frequency v fbx = 0.6v 1.8 2.25 2.7 mhz f sync synchronization frequency 2.25 mhz i lim peak switch current limit v in = 3v, v fbx = 0.5v, duty cycle <35% 1 1.2 1.6 a r ds(on) top switch on-resistance (note 6) 0.35 0.45 bottom switch on-resistance (note 6) 0.30 0.45 i sw(lkg) switch leakage current v in = 5v, v run = 0v, v fbx = 0v 0.01 1 a por power-on reset threshold v fbx ramping up, mode/sync = 0v 8.5 % v fbx ramping down, mode/sync = 0v C8.5 % power-on reset on-resistance 100 200 power-on reset delay 65,536 cycles v run run/ss threshold low 0.3 1 1.5 v run/ss threshold high 2v i run run/ss leakage current 0.01 1 a v mode mode threshold low 0 0.5 v mode threshold high v in C 0.5 v in v
ltc3407a-2 4 3407a2f typical perfor a ce characteristics uw oscillator frequency vs temperature oscillator frequency vs supply voltage efficiency vs input voltage input voltage (v) 2 0 efficiency (%) 10 30 40 50 100 100ma 1ma 70 3 4 3407a2 g04 20 80 90 60 5 6 10ma v out = 1.8v circuit of figure 3 800ma t a = 25 c unless otherwise specified. load step 3407a2 g03 v in = 3.6v v out = 1.8v i load = 50ma to 600ma circuit of figure 3 v out2 100mv/div v out1 200mv/div i l 500ma/div i load 500ma/div 20 s/div burst mode operation 3407a2 g01 v in = 3.6v v out = 1.8v i load = 50ma circuit of figure 3 sw 5v/div v out 50mv/div i l 200ma/div 2 s/div pulse skipping mode 3407a2 g02 v in = 3.6v v out = 1.8v i load = 50ma circuit of figure 3 sw 5v/div v out 10mv/div i l 100ma/div 1 s/div 3407a2 g16 v in = 3.6v v out = 1.8v i load = 500ma circuit of figure 4 v in 2v/div v out1 1v/div i l 500ma/div 1ms/div soft start 2.5 2.4 2.3 2.2 2.1 2.0 frequency (mhz) temperature ( c) C50 25 75 3407a2 g05 C25 0 50 100 125 v in = 3.6v 10 8 6 4 2 0 C2 C4 C6 C 8 C10 frequency deviation (%) supply voltage (v) 2 3407a2 g06 3 456
ltc3407a-2 5 3407a2f efficiency vs load current load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 g14 2.7v 4.2v 3.3v v out = 1.5v burst mode operation line regulation v in (v) 2 v out error (%) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 4 6 3407a2 g15 35 v out = 1.8v i out = 200ma typical perfor a ce characteristics uw efficiency vs load current load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 g13 2.7v 4.2v v out = 1.2v burst mode operation 3.3v efficiency vs load current efficiency vs load current load regulation reference voltage vs temperature r ds(on) vs input voltage r ds(on) vs temperature 0.615 0.610 0.605 0.600 0.595 0.590 0.585 reference voltage (v) temperature ( c) C50 25 75 3407a2 g07 C25 0 50 100 125 v in = 3.6v v in (v) 1 500 450 400 350 300 250 200 46 3407a2 g08 2 3 57 r ds(on) (m ) main switch synchronous switch temperature ( c) C50 550 500 450 400 350 300 250 200 150 100 25 75 3407a2 g09 C25 0 50 100 150 125 r ds(on) (m ) main switch synchronous switch v in = 3.6v v in = 4.2v v in = 2.7v load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 g10 2.7v v out = 2.5v burst mode operation circuit of figure 3 3.3v 4.2v load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 g11 burst mode operation pulse skip mode v in = 3.6v, v out = 1.8v no load on other channel load current (ma) 1 C4 v out error(%) C3 1 0 C1 C2 4 3 2 10 100 1000 3407a2 g12 burst mode operation pulse skip mode v in = 3.6v, v out = 1.8v no load on other channel t a = 25 c unless otherwise specified.
ltc3407a-2 6 3407a2f be synchronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. sw2 (pin 7): regulator 2 switch node connection to the inductor. this pin swings from v in to gnd. por (pin 8): power-on reset. this common-drain logic output is pulled to gnd when the output voltage is not within 8.5% of regulation and goes high after 2 16 clock cycles when both channels are within regulation. run/ss2 (pin 9): regulator 2 enable and soft-start input. forcing this pin to v in enables regulator 2, while forcing it to gnd causes regulator 2 to shut down. connect external rc-network with desired time-constant to enable soft- start feature. this pin must be driven; do not float. v fb2 (pin 10): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. exposed pad (gnd) (pin 11): power ground. connect to the (C) terminal of c out , and (C) terminal of c in . must be soldered to electrical ground on pcb. 1 2 9 10 8 3 4 11 5 C + C + C + C + ea uvdet ovdet 0.6v 7 0.65v 0.55v C + 0.65v uv ov i th switching logic and blanking circuit s r q q rs latch burst C + i comp i rcmp anti shoot- thru burst clamp slope comp en sleep por counter 0.6v ref osc osc regulator 2 (identical to regulator 1) pgood1 pgood2 shutdown v in v in v in 6 regulator 1 sw1 gnd por gnd sw2 3407a2 bd 5 mode/sync v fb1 run/ss1 run/ss2 v fb2 v fb1 (pin 1): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. run/ss1 (pin 2): regulator 1 enable and soft-start input. forcing this pin to v in enables regulator 1, while forcing it to gnd causes regulator 1 to shut down. connect external rc-network with desired time-constant to enable soft- start feature. this pin must be driven; do not float. v in (pin 3): main power supply. must be closely decoupled to gnd. sw1 (pin 4): regulator 1 switch node connection to the inductor. this pin swings from v in to gnd. gnd (pin 5): main ground. connect to the (C) terminal of c out , and (C) terminal of c in . mode/sync (pin 6): combination mode selection and oscillator synchronization. this pin controls the operation of the device. when tied to v in or gnd, burst mode operation or pulse skipping mode is selected, respec- tively. do not float this pin. the oscillation frequency can block diagra w pi fu ctio s uuu
ltc3407a-2 7 3407a2f the ltc3407a-2 uses a constant frequency, current mode architecture. the operating frequency is set at 2.25mhz and can be synchronized to an external oscillator. both channels share the same clock and run in-phase. to suit a variety of applications, the selectable mode/sync pin allows the user to trade-off noise for efficiency. the output voltage is set by an external divider returned to the v fb pins. an error amplifier compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. overvoltage and undervoltage comparators will pull the por output low if the output voltage is not within 8.5%. the por output will go high after 65,536 clock cycles (about 29ms in pulse skipping mode) of achieving regulation. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the reference voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor flows through the bottom switch (n- channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the error amplifier.this amplifier compares the v fb pin to the 0.6v reference. when the load current increases, the v fb volt- age decreases slightly below the reference. this decrease causes the error amplifier to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run/ss pin to ground. low current operation two modes are available to control the operation of the ltc3407a-2 at low currents. both modes automatically switch from continuous operation to the selected mode when the load current is low. to optimize efficiency, the burst mode operation can be selected. when the load is relatively light, the ltc3407a-2 operatio u automatically switches into burst mode operation in which the pmos switch operates intermittently based on load demand with a fixed peak inductor current. by running cycles periodically, the switching losses which are domi- nated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. a voltage comparator trips when i th is below 0.65v, shut- ting off the switch and reducing the power. the output capacitor and the inductor supply the power to the load until i th exceeds 0.65v, turning on the switch and the main control loop which starts another cycle. for lower ripple noise at low currents, the pulse skipping mode can be used. in this mode, the ltc3407a-2 contin- ues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3407a-2 is used at 100% duty cycle with low input voltage (see thermal considerations in the applica- tions information section). low supply operation the ltc3407a-2 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 1.65v to prevent unstable operation. a general ltc3407a-2 application circuit is shown in figure 1. external component selection is driven by the load requirement, and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected.
ltc3407a-2 8 3407a2f input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out / v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maxi- mum rms current must be used. the maximum rms capacitor current is given by: ii vvv v rms max out in out in (C ) where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours life- time. this makes it advisable to further derate the capaci- tor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1 f to 1 f ceramic capacitor is also recom- mended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. table 1. representative surface mount inductors manu- max dc facturer part number value current dcr height taiyo yuden cb2016t2r2m 2.2 h 510ma 0.13 1.6mm cb2012t2r2m 2.2 h 530ma 0.33 1.25mm cb2016t3r3m 3.3 h 410ma 0.27 1.6mm panasonic elt5kt4r7m 4.7 h 950ma 0.2 1.2mm sumida cdrh2d18/ld 4.7 h 630ma 0.086 2mm murata lqh32cn4r7m23 4.7 h 450ma 0.2 2mm taiyo yuden nr30102r2m 2.2 h 1100ma 0.1 1mm nr30104r7m 4.7 h 750ma 0.19 1mm fdk fdkmipf2520d 4.7 h 1100ma 0.11 1mm fdkmipf2520d 3.3 h 1200ma 0.1 1mm fdkmipf2520d 2.2 h 1300ma 0.08 1mm tdk vlf3010at4r7- 4.7 h 700ma 0.28 1mm mr70 vlf3010at3r3- 3.3 h 870ma 0.17 1mm mr87 vlf3010at2r2- 2.2 h 1000ma 0.12 1mm m1r0 applicatio s i for atio wu u u inductor selection although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : = ? ? ? ? ? ? i v fl v v l out o out in ? ?C 1 accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is i l = 0.3 ? i lim , where i lim is the peak switch current limit. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v fi v v out ol out in max = ? ? ? ? ? ? ? ?C () 1 the inductor value will also have an effect on burst mode operation. the transition from low current operation be- gins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this transition to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate much energy, but gener- ally cost more than powdered iron core inductors with similar electrical characterisitics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/emi require- ments than on what the ltc3407a-2 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3407a-2 applications.
ltc3407a-2 9 3407a2f trace inductance can lead to significant ringing. other capacitor types include the panasonic special polymer (sp) capacitors. in most cases, 0.1 f to 1 f of ceramic capacitors should also be placed close to the ltc3407a-2 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. these are tempt- ing for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr generates a loop zero at 5khz to 50khz that is instrumen- tal in giving acceptable loop phase margin. ceramic ca- pacitors remain capacitive to beyond 300khz and usually resonate with their esl before esr becomes effective. also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, tdk, and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. applicatio s i for atio wu u u figure 1. ltc3407a-2 general schematic v out2 run/ss2 v in v in = 2.5v to 5.5v v out1 run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 c in r7 power-on reset c1 c2 l1 l2 r4 r2 r1 r3 c out2 c4 c3 c out1 3407a2 f01 pulseskip* burst* *mode/sync = 0v: pulse skip mode/sync = v in : burst mode r6 r5 output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( v out ) is deter- mined by: ?? + ? ? ? ? ? ? v i esr fc out l o out 1 8 where f o = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.3 ? i lim the output ripple will be less than 100mv at maximum v in and f o = 2.25mhz with: esr cout < 150m once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. alumi- num electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap, offer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density. however, they also have a larger esr and it is critical that they are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signifi- cantly larger esr, and are often used in extremely cost- sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost, but also have the lowest capacitance density, a high voltage and tempera- ture coefficient, and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with
ltc3407a-2 10 3407a2f power-on reset the por pin is an open-drain output which pulls low when either regulator is out of regulation. when both output voltages are within 8.5% of regulation, a timer is started which releases por after 2 16 clock cycles (about 29ms in pulse skipping mode). this delay can be significantly longer in burst mode operation with low load currents, since the clock cycles only occur during a burst and there could be milliseconds of time between bursts. this can be bypassed by tying the por output to the mode/sync input, to force pulse skipping mode during a reset. in addition, if the output voltage faults during burst mode sleep, por could have a slight delay for an undervoltage output condition and may not respond to an overvoltage output. this can be avoided by using pulse skipping mode instead. when either channel is shut down, the por output is pulled low, since one or both of the channels are not in regulation. mode selection & frequency synchronization the mode/sync pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. when this pin is connected to ground, pulse skipping operation is selected which pro- vides the lowest output ripple, at the cost of low current efficiency. the ltc3407a-2 can also be synchronized to another ltc3407a-2 by the mode/sync pin. during synchroni- zation, the mode is set to pulse skipping and the top switch turn-on is synchronized to the rising edge of the external clock. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during applicatio s i for atio wu u u at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 3 times the linear drop of the first cycle. thus, a good place to start is with the output capacitor size of approxi- mately: c i fv out out o droop 3 ? more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely re- quired to supply high frequency bypassing, since the impedance to the supply is very low. a 10 f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3407a-2 develops a 0.6v reference voltage be- tween the feedback pin, v fb , and ground as shown in figure 1. the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 06 1 2 1 . keeping the current small (<5 a) in these resistors maxi- mizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward ca- pacitor c f may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line.
ltc3407a-2 11 3407a2f for approximately a 1ms ramp time, use r ss = 4.7m and c ss = 680pf at v in = 3.3v. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in ltc3407a-2 circuits: 1)v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continu- ous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into applicatio s i for atio wu u u hot swap is a registered trademark of linear technology corporation. this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second- order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feed-forward capacitor can be added to improve the high frequency response, as shown in figure 1. capacitors c1 and c2 provide phase lead by creating high frequency zeros with r2 and r4 respec- tively, which improve the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to applica- tion note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1 f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this prob- lem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap tm controller is designed specifically for this purpose and usually incorpo- rates current limiting, short-circuit protection, and soft- starting. soft-start the run/ss pins provide a means to separately run or shut down the two regulators. in addition, they can option- ally be used to externally control the rate at which each regulator starts up and shuts down. pulling the run/ss1 pin below 1v shuts down regulator 1 on the ltc3407a-2. forcing this pin to v in enables regulator 1. in order to control the rate at which each regulator turns on and off, connect a resistor and capacitor to the run/ss pins as shown in figure 1. the soft-start duration can be calcu- lated by using the following formula: trcin v v s ss ss ss in in = ? ? ? ? ? ? ? ? 1 16 . ()
ltc3407a-2 12 3407a2f where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3407a-2 is in dropout on both channels at an input voltage of 2.7v with a load current of 800ma and an ambient temperature of 70 c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the main switch is 0.425 . therefore, power dissipated by each channel is: p d = i 2 ? r ds(on) = 272mw the ms package junction-to-ambient thermal resistance, ja , is 45 c/w. therefore, the junction temperature of the regulator operating in a 70 c ambient temperature is approximately: t j = 2 ? 0.272 ? 45 + 70 = 94.5 c which is below the absolute maximum junction tempera- ture of 125 c. design example as a design example, consider using the ltc3407a-2 in a portable application with a li-ion battery. the battery provides a v in = 2.8v to 4.2v. the load requires a maxi- mum of 800ma in active mode and 2ma in standby mode. the output voltage is v out = 2.5v. since the load still needs power in standby, burst mode operation is selected for good low load efficiency. first, calculate the inductor value for about 30% ripple current at maximum v in : l v mhz ma v v h = ? ? ? ? ? ? = 25 2 25 360 1 25 42 125 . .? ?C . . . applicatio s i for atio wu u u the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 C d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 4) other hidden losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching fre- quency. other losses including diode conduction losses during dead-time and inductor core losses generally ac- count for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3407a-2 does not dissipate much heat due to its high efficiency. however, in applications where the ltc3407a-2 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150 c, both power switches will be turned off and the sw node will become high impedance. to prevent the ltc3407a-2 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t rise = p d ? ja
ltc3407a-2 13 3407a2f applicatio s i for atio wu u u ltc3407a-2. these items are also illustrated graphically in the layout diagram of figure 2. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 3) and gnd (exposed pad) as closely as possible? this capacitor provides the ac current to the internal power mosfets and their drivers. 2. are c out and l1 closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistor divider formed by r1 and r2 must be connected between the (+) plate of c out and a ground sense line terminated near gnd (exposed pad). the feed- back signals v fb1 and v fb2 should be routed away from noisy components and traces, such as the sw lines (pins 4 and 7), and their traces should be minimized. 4. keep sensitive components away from the sw pins. the input capacitor c in and the resistors r1 to r4 should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available keep the signal and power grounds segregated with small signal components returning to the gnd pin at one point. addtionally the two grounds should not share the high current paths of c in or c out . 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be con- nected to v in or gnd. figure 2. ltc3407a-2 layout diagram (see board layout checklist) run/ss2 v in v in v out2 v out1 run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 c in c4 c5 l1 l2 r4 r2 r1 r3 c out2 c out1 3407a2 f02 bold lines indicate high current paths choosing the next highest standardized inductor value of 2.2 h, results in a maximum ripple current of: = ? ? ? ? ? ? ? = i v mhz h v v m l 25 225 22 1 25 42 204 . .?. ? . . a a for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c ma mhz v f out = 25 800 225 5 25 71 . .?(%?.) . the closest standard value is 10 f. since the output impedance of a li-ion battery is very low, c in is typically 10 f. the output voltage can now be programmed by choosing the values of r1 and r2. to maintain high efficiency, the current in these resistors should be kept small. choosing 2 a with the 0.6v feedback voltage makes r1~300k. a close standard 1% resistor is 280k, and r2 is then 887k. the por pin is a common drain output and requires a pull- up resistor. a 100k resistor is used for adequate speed. figure 3 shows the complete schematic for this design example. the specific passive components chosen allow for a 1mm height power supply that maintains a high efficiency across load. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the
ltc3407a-2 14 3407a2f typical applicatio s u run/ss2 v in v in = 2.5v to 5.5v v out2 = 2.5v at 800ma v out1 = 1.8v at 800ma run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 c1 10 f r5 100k power-on reset c4, 22pf c5, 22pf l1 2.2 h l2 2.2 h r4 887k r2 604k r1 301k r3 280k c3 10 f c2 10 f 3407a2 ta03 c1, c2, c3: taiyo yuden jmk316bj106md l1, l2: tdk vlf3010at-2r2m1r0 figure 3. 1mm height core supply efficiency vs load current figure 4. low ripple buck regulators with soft-start run/ss2 v in v in = 2.5v to 5.5v v out2 = 2.5v at 800ma v out1 = 1.2v at 800ma run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 c in 10 f r7 100k r6 4.7m r5 4.7m power-on reset c1, 22pf c2, 22pf l1 4.7 h l2 4.7 h r4 887k r2 604k r1 604k r3 280k c out2 10 f c4 680pf c3 680pf c out1 10 f 3407a2 ta04 c in , c out1 , c out2: taiyo yuden jmk316bj106ml l1, l2: tdk vlf3012at-4r7m74 efficiency vs load current load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 ta03b 2.5v v in = 3.3v burst mode operation no load on other channel 1.8v load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 ta04b 2.5v v in = 3.3v burst mode operation no load on other channel 1.2v
ltc3407a-2 15 3407a2f package descriptio u mse package 10-lead plastic msop (reference ltc dwg # 05-08-1664) msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699)
ltc3407a-2 16 3407a2f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 related parts part number description comments ltc3405/ltc3405a 300ma (i out ), 1.5mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20 a, synchronous step-down dc/dc converter i sd <1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20 a, synchronous step-down dc/dc converter i sd <1 a, thinsot package ltc3407/ltc3407-2 600ma/800ma (i out ), 1.5mhz/2.25mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, ltc3407-3/ltc3407-4/ dual synchronous step-down dc/dc converter i sd <1 a, ms10e package, dfn package ltc3407a ltc3410/ltc3410b 300ma (i out ), 2.25mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26 a, synchronous step-down dc/dc converter in sc70 i sd <1 a, sc70 package ltc3411 1.25a (i out ), 4mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, synchronous step-down dc/dc converter i sd <1 a, msop-10 package ltc3412/ltc3412a 2.5a (i out ), 4mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, synchronous step-down dc/dc converter i sd <1 a, tssop-16e package ltc3414 4a (i out ), 4mhz, 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64 a, synchronous step-down dc/dc converter i sd <1 a, tssop-28e package ltc3440/ltc3441 600ma/1.2a (i out ), 2mhz/1mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25 a, synchronous buck-boost dc/dc converter i sd <1 a, msop-10 package/dfn package ltc3548/ 400ma/800ma (i out ), 2.25mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, ltc3548-1/ltc3548-2 dual synchronous step-down dc/dc converter i sd <1 a, ms10e package/dfn package lt 0907 ? printed in usa efficiency vs load current efficiency vs load current run/ss2 v in v in = 2.8v to 4.2v v out2 = 3.3v at 200ma v out1 = 1.8v at 800ma run/ss1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407a-2 c1 10 f r5 100k power-on reset c4, 22pf l1 2.2 h l2 10 h r4 887k r2 887k r1 442k r3 196k c3 10 f c6 47 f c2 10 f 3407a ta05 + m1 d1 c1, c2, c3: taiyo yuden jmk316bj106ml c6: sanyo 6tpb47m d1: philips pmeg2010 l1: murata lqh32cn2r2m33 l2: toko a914byw-100m (d52lc series) m1: siliconix si2302 2mm height lithium-ion single inductor buck-boost regulator and a buck regulator u typical applicatio load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 90 80 10 100 1000 3407a2 ta05a 2.8v v out = 3.3v burst mode operation no load on other channel 4.2v 3.6v load current (ma) 1 0 efficiency (%) 30 20 10 70 60 50 40 100 90 80 10 100 1000 3407a2 ta05b 2.8v v out = 1.8v burst mode operation no load on other channel 4.2v 3.6v

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